1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly to a semiconductor memory device such as a dynamic RAM comprising an active pull-up circuit.
2. Description of the Prior Art
In a dynamic MOS RAM, an active pull-up circuit operates after sense amplification of a bit line potential according to stored data in a memory cell, whereby the bit line potential on the side of a high level is pulled up to power supply voltage Vcc.
FIG. 1 is a circuit diagram showing a bit line sense system in a conventional dynamic RAM. Referring to FIG. 1, a pair of bit lines BL and BL are connected to the data buses I/O and I/O through transistors Q.sub.00 and Q.sub.01, respectively. On-off control of the transistors Q.sub.00 and Q.sub.01 is made by on an output of a column decoder 1. Memory cells MC of a one-transistor one-capacitor type for example are connected to each of the bit lines in an alternate manner. FIG. 1 shows only one memory cell for the purpose of simplification of the illustration. Each memory cell MC is connected with an associated word line WL. By selecting suitably word line WL, control is made to connect or disconnect the memory cell MC with or from the associated bit lines BL and BL. A dummy memory cell DMC is connected with each of the bit lines BL and BL. FIG. 1 shows only a dummy memory cell DMC connected with a bit line BL. Each dummy memory cell DMC is connected with an associated dummy word line WLDM. By selecting suitably dummy word line WLDM, control is made to connect or disconnect the dummy memory cell DMC with or from the associated bit lines BL and BL. The bit lines BL and BL are connected to a precharge power supply V.sub.PR through the respective associated transistors Q.sub.PR0 and Q.sub.PR1. On-off control of the transistors Q.sub.PR0 and Q.sub.PR1 is made by a clock signal .phi..sub.PR.
Each pair of bit lines BL and BL are further connected with a sense amplifier SA.sub.0 and an active pull-up circuit AP.sub.0. The sense amplifier SA.sub.0 detects potentials of the associated bit lines after selection of a memory cell and makes the potential of the bit line of the low level correspond to a ground level. Operation of the sense amplifier SA.sub.0 is controlled by a clock signal .phi..sub.S. The active pull-up circuit AP.sub.0 comprises transistors Q.sub.AP0, Q.sub.R0 and a capacitor C.sub.R0 associated with the bit line BL as well as transistors Q.sub.AP1, Q.sub.R1 and a capacitor C.sub.R1 associated with the bit line BL. The transistor Q.sub.AP0 serves to pull up the bit line BL and this transistor is provided between the bit line BL and the power supply Vcc. The capacitor C.sub.R0 serves to increase gate potential of the transistor Q.sub.AP0. An end of the capacitor C.sub.R0 is connected to a gate of the transistor Q.sub.AP0 and the other end thereof receives a clock signal .phi..sub.R. The transistor Q.sub.R0 serves to precharge the capacitor C.sub.R0 with a precharge voltage of the bit line BL and this transistor is provided between the bit line BL and the above stated one end of the capacitor C.sub.R0. A gate of the transistor Q.sub.R0 is connected to the power supply Vcc. The transistors Q.sub.R1, Q.sub.AP1 and the capacitor C.sub.R1 as the circuit elements associated with the bit line BL are provided symmetrically with respect to the transistors Q.sub.R0, Q.sub.AP0 and the capacitor C.sub.R0 as the circuit elements associated with the bit line BL.
In reality, a semiconductor memory includes a plurality of sets of bit lines BL and BL and accordingly memory cells MC are arranged in a matrix.
FIG. 2 is a timing chart for explaining operation of the circuit shown in FIG. 1. Referring to FIG. 2, .phi..sub.S, .phi..sub.R and .phi..sub.PR correspond to the respective clock signals shown in FIG. 1; BL and BL represent change in potential of the bit lines BL and BL; and WL represents change in potential of the word line WL. RAS represents a row address strobe signal. The row address strobe signal RAS is a signal for defining a non-active period and an active period. In the following, the operation of the circuit shown in FIG. 1 will be described with reference to FIG. 2.
In the non-active period, namely, in a period of a high level of the row address strobe signal RAS, the bit lines BL and BL are precharged with a predetermined potential. More specifically, the transistors Q.sub.PR0 and Q.sub.PR1 are turned on in response to the clock signal .phi..sub.PR and the bit lines BL and BL are precharged with a potential V.sub.PR (V.sub.PR =Vcc). At this time, the capacitors C.sub.R0 and C.sub.R1 are charged through the transistors Q.sub.R1 and Q.sub.R2, respectively.
After that, the level of the row address strobe signal RAS falls to start the active period. In the active period, one of the word lines WL and one of the dummy word lines WLDM are selected and the potentials of the respective selected line rise to a high level. By this selection, the contents stored in the associated memory cell MC and the associated dummy memory cell DMC appear on the bit lines and imbalance of potential occurs between the bit lines BL and BL. It is assumed in this case that the potential of the bit line BL becomes lower than the potential of the bit line BL. After the above stated selection, the clock signal .phi..sub.S rises to enable the sense amplifier SA.sub.0. As a result, the bit line BL of the low level becomes equal to the ground level. Consequently, the capacitor C.sub.R1 is discharged to emit the electric charge stored in the capacitor C.sub.R1 to the bit line BL (at the ground level) through the transistor Q.sub.R1 and accordingly potential at a node N.sub.2 (a point of connection between the gate of the transistor Q.sub.AP1 and the capacitor C.sub.R1) becomes equal to the ground level. On the other hand, potential at a node N.sub.1 (a point of connection between the gate of the transistor Q.sub.AP0 and the capacitor C.sub.R0) becomes V.sub.PR -V.sub.R0 (V.sub.R0 being threshold voltage of the transistor Q.sub.R0) After that, the clock signal .phi..sub.R rises to a potential higher than the power supply voltage Vcc to start active pull-up operation. Then, the node N.sub.1 attains a higher potential (a potential higher than the power supply voltage Vcc) by boost effect of the capacitor C.sub.R0 and the transistor Q.sub.AP0 is conducted to a very high degree. Accordingly, the potential of the bit line BL rises to the power supply voltage Vcc. On the other hand, since the potential at the node N.sub.2 is the ground level, the transistor Q.sub.AP1 does not turn on and the potential of the bit line BL remains the ground potential.
Such a conventional circuit as described above is described for example in "A High Performance Sense Amplifier for a 5V Dynamic RAM" by John J. Barnes and John Y. Chan, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-15, No. 5, Oct. 1980 pages 831-839.
In the above described conventional example, the bit lines BL and BL are precharged to the potential V.sub.PR =Vcc before the start of operation of the sense amplifier SAo. However, the precharge voltage is not always set to the power supply voltage Vcc and it is sometimes set to an intermediate value (for example (1/2) Vcc) between the power supply voltage Vcc and the ground potential. Setting of the precharge voltage to such an intermediate value is advantageous for the purposes of decreasing consumption of electric power and applying sense timing at high speed. However, if the precharge voltage of the bit lines BL and BL is set to an intermediate value between the power supply voltage Vcc and the ground potential, the potential at the node N.sub.1 hardly increases, which makes it impossible to perform active pull-up operation. The cause of this phenomenon will be described in detail in the following.
Assuming that the bit lines BL and BL is precharged with a voltage (1/2) Vcc, the gate potential of the transistor Q.sub.R0 becomes equal to the power supply voltage Vcc and the source potential (potential at a terminal connected with the bit line BL) becomes equal to (1/2) Vcc. Accordingly, since forward bias is always applied between the gate and the source of the transistor Q.sub.R0, the transistor Q.sub.R0 is always in the on state. As a result, even if electric charge is stored in the capacitor C.sub.R0 by the increase of the potential of the clock signal .phi..sub.R, the stored electric charge is made to flow out to the bit line BL through the transistor Q.sub.R0. Since the stray capacitance of the bit line BL is considerably large, even if electric charge is stored in the capacitor C.sub.R0 by the clock signal .phi..sub.R, the stored electric charge is immediately made to flow out to the bit line BL. Accordingly, the potential at the node N.sub.1 hardly rises and the transistor Q.sub.AP0 cannot be conducted to a high degree. Thus, the connection between the bit line BL and the power supply Vcc is weakened and active pull-up operation cannot be performed in a satisfactory manner.
As described above, a conventional dynamic RAM involves a disadvantage that active pull-up operation cannot be performed if the precharge level of the bit lines is set to a value lower than the power supply voltage Vcc.